View MB40C338_8992761.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds04-28222-1e fujitsu semiconductor data sheet assp for video applications cmos 3 ch 8-bit 162 msps a/d converter MB40C338 n n n n description MB40C338 is a high-speed 3ch a/d converter using a fast cmos technology. n n n n features ? resolution : 8 bit ? no. of ad channels : 3 ch ? linearity error : 0.40 % (typical) ? maximum conversion rate : 162 msps (minimum) ? power supply voltage : 3.3 v (typical : internal circuit) ? digital input voltage range : ttl level ? digital output voltage range : 3.3 v cmos level ? amp. input voltage range : 0.7 v p - p (typical) ? amp. gain : 1.9 double fixed ? power dissipation : 1100 mw (typical) ? additional features : pll circuit video amp. circuit (1.9 double fixed gain) clamp circuit v rt amp circuit (rgb 3 ch common) v rb amp circuit (rgb 3 ch common) overflow output high impedance output, power down function ? package : lqfp120 (16 mm 16mm, lead pitch : 0.5 mm) n n n n pac k ag e 120-pin plastic lqfp (fpt-120p-m21)
MB40C338 2 n n n n pin assignment (top view) (fpt-120p-m21) rv in v r2 gv in ce bv in v r1 v ref pclp av dd av ss radin av ss gadin v esd badin v rbm v rb v refb rv clp gv clp bv clp av ss av dd cs ck data dv ss dv dd (msb) bd b7 bd b6 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 pv ss pv dd hsync hhold pv dd lpf pv ss r ref v reft v rt v rtm v r3 a vss av dd d vdd dv ss of dsync dsyncb cout expclk expclkb exclk adclka adclkb clk clkb dv dd dv ss a vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 bd b5 bd b4 bd b3 bd b2 bd b1 (lsb) bd b0 dv ss dv dd (msb) bd a7 bd a6 bd a5 bd a4 bd a3 bd a2 bd a1 (lsb) bd a0 av dd av ss dv ss dv dd (msb) gd b7 gd b6 gd b5 gd b4 gd b3 gd b2 gd b1 (lsb) gd b0 dv dd dv ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 rd a0 (lsb) rd a1 rd a2 rd a3 rd a4 rd a5 rd a6 rd a7 (msb) dv dd dv ss av ss av dd rd b0 (lsb) rd b1 rd b2 rd b3 rd b4 rd b5 rd b6 rd b7 (msb) dv dd dv ss gd a0 (lsb) gd a1 gd a2 gd a3 gd a4 gd a5 gd a6 gd a7 (msb)
MB40C338 3 n n n n pin description note: the values in parentheses are standard. (continued) pin no. symbol description 9, 23, 47, 79, 107 av dd analog power supply ( + 3.3 v) 28, 38, 50, 59, 70, 82, 93, 106 dv dd digital power supply ( + 3.3 v) 116, 119 pv dd pll power supply pin ( + 3.3 v) 14 v esd digital input power supply for protect device ( + 3.3 v or + 5 v) 10, 12, 22, 48, 80, 91, 108 av ss analog power supply ground pin (0 v) 27, 37, 49, 60, 69, 81, 92, 105 dv ss digital power supply ground pin (0 v) 114, 120 pv ss pll power supply ground pin (0 v) 1 3 5 rv in gv in bv in 1.9 double amp. input pin 11 13 15 radin gadin badin a/d converter input pin please set these pins to open usually. 19 20 21 rv clp gv clp bv clp clamp voltage setting input pin 110 v rtm reference voltage output pin on top side 111 v rt reference voltage input pin on top side 112 v reft reference voltage generator output pin on top side 16 v rbm reference voltage output pin on bottom side 17 v rb reference voltage input pin on bottom side 18 v refb reference voltage generator output pin on bottom side 6 2 109 v r1 v r2 v r3 reference 1/4 voltage output pin (add 0.1 m f for av ss ) reference 1/2 voltage output pin (add 0.1 m f for av ss ) reference 3/4 voltage output pin (add 0.1 m f for av ss ) 25 ck serial data transfer clock input pin 26 data serial data input pin 24 cs chip select signal input pin it is possible to input to the shift register at cs falling the content of the shift register is executed at cs rising. 98 exclk clock input pin for a/d converter (cmos level) fix to l level when unused.
MB40C338 4 (continued) note: the values in parentheses are standard. parameter symbol description 99 expclkb differential clock (negative-phase) input pin for a/d converter fix to h level when unused. pecl level 100 expclk differential clock (positive-phase) input pin for a/d converter fix to l level when unused. 8 pclp clamp pulse input pin 4ce power down at ce input h (internal pull-up resistor) 113 r ref internal current setting pin (add 12 k w for av ss ) 103 dsync delay sync signal output pin 102 dsyncb inverted delay sync signal output pin 95 clk clock output pin (see n timing diagram.) 94 clkb 97 adclka 96 adclkb 83 to 90 61 to 68 39 to 46 rd a7 to rd a0 gd a7 to gd a0 bd a7 to bd a0 digital output pin (port a) rd a7 , gd a7 , bd a7 : msb rd a0 , gd a0 , bd a0 : lsb 71 to 78 51 to 58 29 to 36 rd b7 to rd b0 gd b7 to gd b0 bd b7 to bd b0 digital output pin (port b) rd b7 , gd b7 , bd b7 : msb rd b0 , gd b0 , bd b0 : lsb 101 cout pll counter output pin 115 lpf external capacitor/resistor connection pin 117 hhold phase detector operation is hold by input h level 118 hsync horizontal sync signal input pin 7v ref internal voltage output pin (add 3.3f for av ss ) 104 of overflow output pin (h level output at overflow)
MB40C338 5 n n n n block diagram pclp radin rv in rv clp ce hsync hhold cout lpf expclk expclkb exclk pv ss pv dd ck cs clkb clk dsyncb dsync dv ss av ss adclkb adclka of v r3 v r2 v r1 v rbm v rb v rt v rtm dv dd av dd v refb v reft v esd rd b0 ~ rd b7 rd a0 ~ rd a7 data rr amp + clamp + a/d 1.9 a ch b ch 8 bit a/d 8 bit a/d 8 8 8 8 buffer buffer buffer buffer buffer buffer buffer buffer 11 bit shift counter (12 bit) filter 3 ch (1 bit) 2 bit (1 ~ 1/8) div mux vco delay reset cp pd pol 2 bit (0 ~ 3 clk) 1/2 clk delay vref amp block pll block 6 bit (32 divide, 2clk)
MB40C338 6 n n n n absolute maximum ratings *1 : do not exceed +4.0 v. *2 : do not exceed +7.0 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit min. max. power supply voltage av dd , dv dd , pv dd - 0.3 + 4.0 v v esd - 0.3 + 7.0 v input/output voltage rv in , gv in , bv in , radin, gadin, badin, rv clp , gv clp , bv clp , v rt , v rtm , v reft , v rb , v rbm , v refb , v r1 , v r2 , v r3 v ref , r ref - 0.3 av dd + 0.3* 1 v rd a0 to rd a7 , rd b0 to rd b7 , gd a0 to gd a7 , gd b0 to gd b7 , bd a0 to bd a7 , bd b0 to bd b7 , dsync, dsyncb, of, cout, clk, clkb, adclka, adclkb - 0.3 dv dd + 0.3* 1 v lpf - 0.3 pv dd + 0.3* 1 v ck, data, cs , expclkb, expclk, pclp, ce , exclk, hhold, hsync - 0.3 v esd + 0.3* 2 v storage temperature t stg - 55 + 125 c
MB40C338 7 n n n n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. typ. max. power supply voltage av dd , dv dd 3.00 3.30 3.60 v pv dd 3.00 3.30 3.60 v v esd 3.00 ? 5.25 v a/d converter input voltage v adin v rb ? v rt v analog reference voltage: t v rt ? 2.2 av dd - 0.6 v analog reference voltage: b v rb 0.6 0.7 ? v analog reference voltage range v rt - v rb 1.0 1.5 1.8 v video amp input voltage v in ( p - p ) 0.5 ? 0.9 v p - p clamp input voltage v clp 0.6 v rb 1.7 v digital h level input voltage v ihd 2.5 ? v esd v digital l level input voltage v ild 0 ? 0.5 v digital h level output current i ohd - 400 ??m a digital l level output current i old ?? 1.6 ma pll counter p c 100 ? 4095 ? hsync input frequency range f hsync 10 ? 100 khz hhold set up time t shhold 20 ?? ns hhold hold time t hhhold 20 ?? ns clamp pulse width t wclp 0.5 ??m s ck clock pulse width t wckl , t wckh 100 ?? ns data set up time t sdata 30 ?? ns data hold time t hdata 30 ?? ns cs set up time t scs 50 ?? ns cs hold time t hcs 50 ?? ns cs h level hold time t wcsh 100 ?? ns operating temperature range ta - 20 ? 70 c
MB40C338 8 n n n n electrical characteristics 1. dc characteristics in analog section ? power supply current (av dd = dv dd = pv dd = 3.0 v to 3.6 v, v esd = 3.0 v to 5.25 v, ta = - 20 c to + 70 c) ?a/d block (av dd = dv dd = pv dd = 3.0 v to 3.6 v, v esd = 3.0 v to 5.25 v, ta = - 20 c to + 70 c) ? video amp block (av dd = dv dd = pv dd = 3.0 v to 3.6 v, v esd = 3.0 v to 5.25 v, ta = - 20 c to + 70 c) ? clamp block (av dd = dv dd = pv dd = 3.0 v to 3.6 v, v esd = 3.0 v to 5.25 v, ta = - 20 c to + 70 c) ? pll block (av dd = dv dd = pv dd = 3.0 v to 3.6 v, v esd = 3.0 v to 5.25 v, ta = - 20 c to + 70 c) parameter symbol value unit min. typ. max. analog power supply current ai dd ? 220 310 ma digital power supply current di dd ? 100 110 ma power supply current pll section (@ f vcoh = 162 mhz, icp = 0.5 ma, div = 1/1) pi dd ? 16 20 ma standby current i sb ? 10 ? ma parameter symbol value unit min. typ. max. resolution ?? 8 ? bit linearity error (dc accuracy) le - 0.8 0.4 + 0.8 % differential linearity error (dc accuracy) dle - 0.36 0.2 + 0.65 % reference voltage : t v reft 0.63 av dd 0.67 av dd 0.70 av dd v reference voltage : b v refb 0.18 av dd 0.21 av dd 0.24 av dd v analog reference voltage input current i rt , i rb ? 520 m a parameter symbol value unit min. typ. max. video amp gain g amp 1.8 1.9 2.0 ? video amp output voltage range v ampout 0.5 ? av dd - 0.6 v video amp frequency width bw ? 250 ? mhz video amp input capacity c vin ? 5 ? pf parameter symbol value unit min. typ. max. v clp input current i clp ? 520 m a clamp voltage v clamp v clp - 0.1 v clp v clp + 0.1 v parameter symbol value unit min. typ. max. clk jitter (@ f hsync = 79.98 khz, f clk = 135.0 mhz) p tj ? 1.0 1.5 ns
MB40C338 9 2. dc characteristic in digital section (av dd = dv dd = pv dd = 3.0 v to 3.6 v, v esd = 3.0 v to 5.25 v, ta = - 20 c to + 70 c) 3. switching characteristics (av dd = dv dd = pv dd = 3.0 v to 3.6 v, v esd = 3.0 v to 5.25 v, ta = - 20 c to + 70 c) n n n n digital output buffer load circuit n n n n mode setting parameter symbol value unit min. typ. max. digital input current i id - 20 ? 5 m a digital h level output voltage v ohd dv dd - 0.4 ?? v digital l level output voltage v old ?? 0.4 v parameter symbol value unit min. typ. max. a/d maximum conversion rate f s 162 ?? msps aperture time t ad ? 1.5 ? ns vco oscillation frequency vcol f vcol 75 ? 140 mhz vcoh f vcoh 85 ? 162 mhz clk output delay time t pd ( hsync - clk ) 1.0 2.0 4.0 ns digital output delay time t pd ( clk - adclk2 ) 0.0 1.0 2.0 ns t pd ( clk - data2 ) 2.5 4.0 6.0 ns dsync output delay time t pd ( clk - dsync ) 0.5 1.5 2.0 ns symbol setting mode ce h aii function power off l operation mode c l = 15 pf dv ss to the measurement point measurement point note: c l includes a stray capacitance of a probe and a fixture.
MB40C338 10 n n n n serial data setting (msb fast) *1 : setting at 6bit, resolution : 1/32 clk, setting range : 0 to 63/32 clk *2, *3, *4 : see under table example: input at 16 bit setting 0 (0, 0) 1 (1, 0) 2 (0, 1) 3 (1, 1) dsync delay* 2 0 clk 1 clk 2 clk 3 clk charge pump current* 3 0.1 ma 0.5 ma 1.0 ma ? divider setting* 4 1/1 1/2 1/4 1/8 (address) (data) lsb msb resd0d1d2d3d4d5d6d7d8d9d10 function 1100 0 0 0 0 0 0 1 0 counter low ranking 8 bit 2010 0 0 0 0 x x x x counter high ranking 4 bit 3 110 0 0 0 0 0 0 1 0 clk delay adjust* 1 : t d = n/ (32 f clk ) 110000000 10 hsync polarity : 0 = through, 1 = inversion 1100000001 0 a/d converter output : 0 = operation, 1 = high impedance 4 001 0 0 0 0 0 0 1 0 clk output : 0 = on, 1 = l 0010 000001 0clkb output : 0 = on, 1 = l 00100 0 0 0 0 1 0 dsync output : 0 = on, 1 = l 001000 0 0 0 1 0 dsyncb output : 0 = on, 1 = l 0010000 0 0 1 0 adclka output : 0 = on, 1 = l 00100000 0 1 0 adclkb output : 0 = on, 1 = l 001000000 1 0dsync delay* 2 : 0, 1, 2, 3 5 101 0000001 0 clk change : 0 = vco, 1 = external clock 1010 000001 0 external clock input : 0 = cmos, 1 = pecl 10100 0 0 0 0 1 0 counter operation : 0 = on, 1 = off 101000 0 001 0 charge pump current* 3 : 0.1 ma, 0.5 ma, 1 ma 10100000 0 1 0 vco select : 0 = vcol, 1 = vcoh 101000000 1 0 divider setting* 4 : 1, 1/2, 1/4, 1/8 1 msb (5 bit) (8 bit) data (3 bit) lsb data input cs input invalid data address
MB40C338 11 n n n n recommended value of serial data setting vco select : vcoh (f vco = 85 mhz to 162 mhz) vcol (f vco = 75 mhz to 140 mhz) f clk = f hsync counter f vco = f hsync counter/divider f clk (mhz) f hsync (khz) counter icp (ma) vco select divider f vco (mhz) uxga 162.000 75.000 2160 0.5 vcoh 1/1 162.000 sxga 157.500 91.146 1728 0.5 vcoh 1/1 157.500 135.000 81.130 1664 0.5 vcoh or vcol 1/1 135.000 108.000 64.904 1664 0.5 vcoh or vcol 1/1 108.000 xga 94.500 68.677 1376 0.5 vcoh or vcol 1/1 94.500 78.750 60.023 1312 0.5 vcol 1/1 78.750 75.000 56.476 1328 0.5 vcoh 1/2 150.000 65.000 48.363 1344 0.5 vcoh or vcol 1/2 130.000 svga 56.250 53.674 1048 0.5 vcoh or vcol 1/2 112.500 50.000 48.077 1040 0.5 vcoh or vcol 1/2 100.000 49.500 46.875 1056 0.5 vcoh or vcol 1/2 99.000 40.000 37.879 1056 0.5 vcol 1/2 80.000 vga 36.000 43.269 832 0.5 vcoh 1/4 144.000 31.500 37.861 832 0.5 vcoh or vcol 1/4 126.000 25.175 31.469 800 0.5 vcoh or vcol 1/4 100.700 25.149 31.436 800 0.5 vcoh or vcol 1/4 100.596 pal 29.375 15.625 1880 0.5 vcoh or vcol 1/4 117.500 22.031 15.625 1410 0.5 vcoh or vcol 1/4 88.125 14.688 15.625 940 0.5 vcoh or vcol 1/8 117.500 ntsc 24.545 15.734 1560 0.5 vcoh or vcol 1/4 98.180 18.409 15.734 1170 0.5 vcoh 1/8 147.270 12.273 15.734 780 0.5 vcoh or vcol 1/8 98.180
MB40C338 12 n n n n timing diagram ? demultiplex output (in-phase) mode ? adin input: sampling at clk rising (at clkb falling) ?d a0 to d a7 : output (after 6 clk + t pd ( clk - data2 ) from sampling ) at clk rising (at clkb falling) ?d b0 to d b7 : output (after 5 clk + t pd ( clk - data2 ) from sampling ) at clk rising (at clkb falling) t pd (hsync-clk) t pd (clk-dsync) t ad t pd (clk-adclk2) t pd (clk-data2) n x x x x x x x x x x x x x x x n n + 1 n n + 2 n + 3 n + 2 n + 1n + 2n + 3n + 4n + 5n + 6n + 7n + 8n + 9 hsync input clkb output clk output dsync output adclka output adclkb output adin input d a0 to d a7 output d b0 to d b7 output of output v ihd v ild v ohd v old v ohd v ohd v ohd v ohd v ohd v ohd v old v old v old v old v old v old
MB40C338 13 n n n n clamp and amp operation - + + - rv in 10 m f r1 1.9 r2 gv in pclp gadin v rt gv clp v rb 0.7 v p-p rv clp radin amp/clamp circuit image signal clamp pulse internal bias (0.6 avdd) < for example, sync on g signal input > 1.33 v p - p contrast adjust : controlling the voltage difference between vrt and vrb (typ : v rt - v rb = 1.33 v) brightness adjust : controlling the voltage difference between vclp and vrb (typ : v clp = v rb )
MB40C338 14 n n n n clamp signal and hold signal n n n n serial data transfer timing t hhhold t shhold t hhhold t shhold t wclp hsync input hhold input pclp input clk output t wckl t wckh t sdata t hdata t hcs t scs t wcsh d10 d9 d8 d7 d1 d0 data input ck input cs input
MB40C338 15 n n n n typical application (lsb) rd a0 90 rd a1 89 rd a2 88 rd a3 87 rd a4 86 rd a5 85 rd a6 84 (msb) rd a7 83 dv dd 82 dv ss 81 av ss 80 av dd 79 (lsb) rd b0 78 rd b1 77 rd b2 76 rd b3 75 rd b4 74 rd b5 73 rd b6 72 (msb) rd b7 71 dv dd 70 dv ss 69 (lsb) gd a0 68 gd a1 67 gd a2 66 gd a3 65 gd a4 64 gd a5 63 gd a6 62 (msb) gd a7 61 pv ss 120 pv dd 119 hsync 118 hhold 117 pv dd 116 lpf 115 pv ss 114 r ref 113 v reft 112 v rt 111 v rtm 110 v r3 109 av ss 108 av dd 107 dv dd 106 dv ss 105 of 104 dsync 103 dsyncb 102 cout 101 expclk 100 expclkb 99 exclk 98 adclka 97 adclkb 96 clk 95 clkb 94 dv dd 93 dv ss 92 av ss 91 31 bd b5 32 bd b4 33 bd b3 34 bd b2 35 bd b1 36 bd b0 (lsb) 37 dv ss 38 dv dd 39 bd a7 (msb) 40 bd a6 41 bd a5 42 bd a4 43 bd a3 44 bd a2 45 bd a1 46 bd a0 (lsb) 47 av dd 48 av ss 49 dv ss 50 dv dd 51 gd b7 (msb) 52 gd b6 53 gd b5 54 gd b4 55 gd b3 56 gd b2 57 gd b1 58 gd b0 (lsb) 59 dv dd 60 dv ss 1 rv in 2 v r2 3 gv in 4 ce 5 bv in 6 v r1 7 v ref 8 pclp 9 av dd 10 av ss 11 radin 12 av ss 13 gadin 14 v esd 15 badin 16 v rbm 17 v rb 18 v refb 19 rv clp 20 gv clp 21 bv clp 22 av ss 23 av dd 24 cs 25 ck 26 data 27 dv ss 28 dv dd 29 bd b7 (msb) 30 bd b6 + + + + + dv ss (0 v) dv dd ( + 3.3 v) expclk expclkb exclk v rt 12 k w 0.001 m f 0.1 m f 1.6 k w hhold hsync + pv dd ( + 3.3 v) pv ss (0 v) av ss (0 v) av dd ( + 3.3 v) rv in ce gv in bv in pclp v rb /v clp serial data + 3.3 v or + 5 v 75 w` 75 w 100 m f 10 m f 10 m f 10 m f (MB40C338) 100 m f 100 m f note : unexpresstion capacitance values are all 1 m f 75 w
MB40C338 16 n n n n usage precautions be sure to ground the pins of av dd , dv dd , pv dd , v esd , v rtm , v rbm , v r1 , v r2 , v r3 and v ref via high-frequency capacitor. place the high-frequency capacitor as close as possible to the pin. n n n n ordering information part number package remark MB40C338pfv 120-pin plastic lqfp (fpt-120p-m21)
MB40C338 17 n n n n package dimension 120-pin plastic lqfp (fpt-120p-m21) c 1998 fujitsu limited f120033s-2c-2 1 30 60 31 90 61 120 91 16.00?.10(.630?004)sq 18.00?.20(.709?008)sq 0.50(.020) 0.22?.05 (.009?002) m 0.08(.003) index .006 ?001 +.002 ?.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?004 +.008 ?.10 +0.20 1.50 details of "a" part 0~8 (mounting height) 0.45/0.75 (.018/.030) 0.25(.010) (.004?002) 0.10?.05 (stand off) dimension in mm (inches)
MB40C338 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0009 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB40C338

	To Download MB40C338 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .